Senior Digital Verification Engineer
Silicon Vision
3d ago

General Description

Candidate is responsible for participating in the verification of the digital part in the mixed signal IPs and digital controller IPs.

He will gather verification requirements , contribute in the verification planning , implement the verification environment , running simulations and achieve coverage targets.

Candidate also shall perform post APR simulations and Co-simulation activities for our Mixed signal IPs.


  • Extract verification requirements from system specification.
  • Contribute in generating the verification plan for block level and system level.
  • Contribute in architecting the verification environment which is mapped from the verification plan.
  • Implement the verification environment using UVM.
  • Debug test failures and work with designers to develop fixes.
  • Work on achieving targeted coverage goal for the verification sign off.
  • Perform post APR simulations.
  • Perform Co-simulation activities and work with analog and digital teams to gather Co-sim requirements and develop fixes on the interaction between analog and digital parts in the IP.
  • Responsible for conducting customer meetings and communicate regularly with customers.
  • Conduct induction training for newcomers.
  • Provide guidance and mentoring to junior engineer.
  • Attend potential customers meetings to answer the technical questions.

    Knowledge Education B.Sc. / M.Sc. in Electronics or Computer Engineering Years of Experience + 4 years of experience Other Knowledge / Studies

  • Other Knowledge / Studies
  • Skills Language Skills Oral and written fluency in English Computer Skills Microsoft office Other Skills

  • Excellent Knowledge of coverage driven verification concepts.
  • Excellent Knowledge of any of the advanced verification methodologies (OVM / UVM / VMM).
  • Excellent knowledge in verification environment architecting, designing and implementation.
  • Good experience in developing and maintaining both block level and top-level verification environments for digital systems.
  • Excellent debugging skills in both functional and gate level simulations.
  • Experience with Assertion Based Verification languages (SVA, PSL ).
  • Knowledge of any scripting language ( PERL ,TCL , Shell script , )
  • Experience with power aware verification and knowledge of writing of writing UPF would be an asset.
  • Experience with Formal Verification would be an asset.
  • Knowledge of Co-simulation for digital and analog parts of the system using AMS simulators.
  • Abilities

  • Self-driven and Motivated
  • High communication skills
  • Detailed Oriented
  • Ownership and dedication
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